1. Field of the Invention
The present invention is generally in the field of electrical circuits and systems. More specifically, the present invention is in the field of clock generation in electrical circuits and systems.
2. Background Art
In system design, it is often necessary to emulate the performance of a dual port memory device using a single port core memory by employing a scheme to achieve a core clock frequency approximately twice that of the system clock. Conventional approaches to achieving this outcome may attempt to do so by utilizing both the rising edge of a system clock signal and the falling edge of the same signal, to trigger core clock signals, thereby producing two core clock signals per one system clock signal. The efficacy of that conventional approach is dependent, however, on the duty cycle of the system clock. Where, for example, the duty cycle of the system clock approximates a fifty percent duty cycle, i.e. the system clock has both its ON and OFF intervals lasting approximately half of the system clock cycle time, the conventional approach may provide an acceptable solution.
More disadvantageous, however, is the situation in which the system clock duty cycle deviates from approximately fifty percent. In that case, the deviation may produce core clock ON or OFF intervals having undesirable durations, being either too brief, or too protracted. In addition, a system clock duty cycle deviation from approximately fifty percent may produce undesirable asymmetry between the ON interval and the OFF interval of the core clock. When the deviation is substantial enough, the minimum cycle time requirement of a core clock being regulated by this procedure may not be met. Consequently, the described conventional approach, in which the core clock signals depend on the duty cycle of the system clock, is at least problematic, and may result in undesirable performance consequences.
Thus, there is a need in the art for a solution that uses a system clock to regulate a core clock, while eliminating the performance uncertainties flowing from dependence of the core clock signals on the system clock duty cycle.